The flat panel display devices possess many merits of thin frame, power saving, no radiation, etc. and have been widely used. The present flat panel display devices at present mainly comprise the Liquid Crystal Display (LCD) and the Organic Light Emitting Display (OLED).
At present, in the active array flat panel display device, the TFT substrate generally utilizes the single-gate oxide semiconductor thin film transistor (Single-Gate TFT). The dual gate oxide semiconductor thin film transistor (Dual-Gate) possesses better performance than the single gate oxide semiconductor thin film transistor. For example, the electron mobility is higher, and the current of activation state is larger, and the subthreshold swing is smaller, and the stability and the uniformity of the threshold voltage are better, and the gate voltage bias and the light stability are better. In the OLED display device, the importance of the threshold voltage is significant. The stable, uniform threshold voltage can make the display brightness of the OLED be more even and the display quality be higher.
In the manufacture process of the OLED, for reducing the difficulty of the manufacture and preventing the deterioration and uneveness of the chromaticity and brightness of the organic light emitting material, the display method of white organic light emitting diode in cooperation with the Color Filter (CF) is commonly utilized. The manufactured of the color filter in the white light OLED display device is mainly accomplished in the array manufacture process of the TFT substrate. Namely, the Color Filter On Array (COA) technology is utilized.
A manufacture method of a dual gate oxide semiconductor TFT substrate applicable for the OLED mainly comprises steps of:
Step 1, as shown in FIG. 1, providing a substrate 100, and deposing a first metal layer on the substrate 100, and implementing pattern process to the first metal layer with a first photo process to form a first bottom gate 210 and a second bottom gate 220; and deposing a bottom gate isolation layer 310 on the first bottom gate 210, the second bottom gate 220 and the substrate 100;
Step 2, as shown in FIG. 2, implementing pattern processes to the bottom gate isolation layer 310 with a second photo process to expose a portion of the first bottom gate 210;
Step 3, as shown in FIG. 3, deposing an oxide semiconductor layer on the bottom gate isolation layer 310, and implementing patterning process to the oxide semiconductor layer with a third photo process to obtain a first oxide semiconductor layer 410 and a second oxide semiconductor layer 420respectively above the first bottom gate 210, the second bottom gate 220;
Step 4, as shown in FIG. 4, deposing an etching stopper layer on the first oxide semiconductor layer 410 and the second oxide semiconductor layer 420 and the bottom gate isolation layer 310, and implementing patterning process to the etching stopper layer with a fourth photo process to form an etching stopper layer 500;
Step 5, as shown in FIG. 5, deposing a second metal layer on the etching stopper layer 500, and implementing patterning process to the second metal layer with a fifth photo process to form a first source 610, a first drain 620, a second source 630, a second drain 640; the second source 630 contacts with the first bottom gate 210;
Step 6, as shown in FIG. 6, deposing a passivation layer on the first source 610, the first drain 620, the second source 630, the second drain 640 and the etching stopper layer 500, and implementing patterning process to the passivation layer with a sixth photo process to form a passivation layer 700, and forming a via hole 720 above the first source 610;
Step 7, as shown in FIG. 7, deposing a third metal layer on the passivation layer 700, and implementing patterning process to the third metal layer with a seventh photo process to form a first top gate 810 and a second top gate 820;
Step 8, as shown in FIG. 8, deposing a color resist layer on the first top gate 810, the second top gate 820 and the passivation layer 700, and implementing patterning processes to the color resist layer with eighth, ninth, tenth photo processes to form red/green/blue color resist layers 900;
Step 9, as shown in FIG. 9, deposing a first flat layer on the red/green/blue color resist layers 900, and implementing patterning process to the first flat layer with an eleventh photo process to form the first flat layer 1000;
Step 10, as shown in FIG. 10, deposing an ITO layer on the first flat layer 1000, and implementing patterning process to the ITO layer to form an anode 1100 with a twelfth photo process, and the anode 1100 contacts with the first source 610 through the via hole 720;
Step 11, as shown in FIG. 11, deposing a second flat layer on the first flat layer 1000 and the anode 1100, and implementing patterning process to the second flat layer with a thirteenth photo process to form a second flat layer 1200.
The aforesaid manufacture process of the oxide semiconductor TFT substrate applicable for the OLED requires thirteen photo processes in total. The manufacture process is complicated and the production efficiency is lower and the manufacture cost is higher.